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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:21:21 03/03/2012 
-- Design Name: 
-- Module Name:    meminstrucciones - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.all;
use work.cinstructions.all;

entity instructionsMem is

	port(
		clk_i : in STD_LOGIC;
		instr_cyc_i : in STD_LOGIC;		
		instr_stb_i : in STD_LOGIC;
		instr_ack_o : out STD_LOGIC;
		instr_addr_i : in STD_LOGIC_VECTOR (9 downto 0);		
		instr_word_o : out STD_LOGIC_VECTOR (17 downto 0)
		);

end instructionsMem;

architecture Behavioral of instructionsMem is

		
constant instructions_memory:instr_memory_type:= program;


begin

	instr_word_o <= instructions_memory(conv_integer(instr_addr_i));
	
	instr_ack_o <= instr_stb_i and instr_cyc_i;

end Behavioral;

